The present invention relates to a nonvolatile semiconductor memory device using a ferroelectric capacitor, a method of driving the same, and various systems each having the semiconductor memory device.
In recent years, a nonvolatile memory (FRAM) using a ferroelectric capacitor has received a great deal of attention as one of semiconductor memories. Since the FRAM is advantageous in that it is nonvolatile, the number of times of rewrite access is 10.sup.12, the read/write time almost equals that of a DRAM, and it can operate at a low voltage of 3 to 5V, the FRAMs may replace all memory markets.
Along with developments, the cell size of the FRAM has been reduced by simplifying and micropatterning the cell structure, as in development of DRAMs. FIG. 1A shows the memory cell of a conventional DRAM having a 1-transistor/1-capacitor structure. FIG. 1B shows the memory cell of a conventional FRAM having a 1-transistor/1-capacitor structure. Reference symbol WL denotes a word line; BL, a bit line; SN, a storage node; and PL, a plate electrode.
The FRAM memory cell basically has the same structure as that of the DRAM. The FRAM is different from the DRAM in the following two points. (1) Although the DRAM uses a dielectric without any spontaneous dielectric polarization as a capacitor, the FRAM uses a ferroelectric capacitor. (2) In the DRAM, the plate electrode at one terminal of the capacitor is fixed at (1/2)Vcc. However, in the FRAM, the plate electrode potential is changed within the range of 0V to Vcc.
For (2), however, the scheme of changing the plate electrode potential is being replaced with a scheme of fixing the plate electrode at (1/2)Vcc.
Therefore, the FRAM equals the DRAM except for (1). The FRAM also has the same cell array structure as that of the DRAM. The FRAM has a folded bit line (BL) structure as shown in FIG. 1C. The minimum cell size at this time is represented as follows: EQU 2F.times.4F=8F.sup.2
In FIG. 1C, reference symbol MC denotes a memory cell; SA, a sense amplifier; and F, a minimum processing size. BL and BL in FIG. 1C denote a bit line pair.
The principle of the operation of the FRAM will be briefly described with reference to FIGS. 2A and 2B.
In the DRAM, the cell transistor is turned on, and Vcc or a voltage of 0V is applied to the cell capacitor to write charges, thereby storing store data "0" or "1". In reading, the cell transistor is turned on to read out the charges. In the DRAM, the accumulated charges (polarization value C!) are proportional to the voltage applied across the cell capacitor, as shown in FIG. 2A. For this reason, when the applied voltage becomes 0V due to a leakage current at the p-n junction of the cell transistor or the like, the polarization value also becomes 0 C, and the information is destroyed.
In the FRAM, however, the polarization characteristics have a hysteresis. A case wherein, after power-ON, the plate (PL) voltage is 0V, the storage node (SN) potential is 0V, and data "0" has been written in the cell will be considered. Since the plate electrode potential is 0V, and the storage node potential is 0V, the voltage applied to the ferroelectric capacitor is 0V, and the polarization value is at a position D of the remnant polarization (=-Pr) in FIG. 2B. When the memory cell data is to be read out, the bit line (BL) potential is precharged to 0V, the cell transistor is turned on, and the plate electrode voltage is raised to Vcc. Since the bit line capacity is larger than the storage node capacity, a voltage -Vcc is applied between the bit line and the plate electrode. The polarization value changes from the point D to a point C, so that a potential corresponding to the small saturation polarization difference Ps-Pr is read out to the bit line.
When data "1" has been written in the cell, the voltage -Vcc is applied between the bit line and the plate electrode, as in the above-described case. Accordingly, polarization inversion from a point B to the point C occurs, and charges in a large amount corresponding to Ps+Pr are read out to the bit line.
The reference bit line potential is raised to the potential at which charges corresponding to Ps are read out. In reading the data "1", a potential difference corresponding to (Ps+Pr)-(Ps)=Pr is generated between the reference bit line and the bit line. In reading the data "0", a potential difference corresponding to (Ps-Pr)-(Ps)=-Pr is generated between the reference bit line and the bit line. This result (potential difference) is amplified by the sense amplifier. The readout result is amplified by the sense amplifier. For the data "1", the bit line is set at Vcc. For the data "0", the bit line is set at 0V.
To rewrite the memory cell data, the plate electrode voltage is lowered to 0V again. At this time, the data "0" returns from the point C to the point D at BL-PL=0V, and the data "1" returns from the point C to the point D and then polarization-inverted to a point A at BL-PL=Vcc. Thereafter, the cell transistor is turned off. The data "1" moves from the point A to the point B when the storage node potential lowers to 0V due to the leakage current and stops at the point B. FIG. 3A shows the series of operations.
The largest difference between the operation of the FRAM and that of the DRAM is as follows. In the FRAM, no data is read out only by turning on the cell transistor and short-circuiting the bit line BL and the storage node SN. No charges are removed unless the direction of polarization is reversed to that for writing the charges between the bit line BL (storage node SN) and the plate electrode PL. Accordingly, a plate electrode operation with a large load capacity is required, and read/write access takes a long time. This is the disadvantage of the FRAM.
To solve this problem, the scheme of fixing the plate electrode potential at (1/2)Vcc is proposed, as described above. FIGS. 3B and 3C show the operations of these schema. In recall after power-ON (on the left side of FIGS. 3B and 3C), the plate electrode PL is precharged to (1/2)Vcc, and the bit line BL is precharged to 0V. The word line WL is selected to turn on the cell transistor. At this time, a voltage of -(1/2)Vcc is applied between the bit line BL and the plate electrode PL. As shown in FIG. 2B, the data "1" is polarization-inverted from the point B to the point C, the data "0" moves from the point D to the point C without polarization inversion, and the accumulated charges are read out to the bit line BL. The information "0" or "1" is read out depending on the presence/absence of polarization inversion. The readout result is amplified by the sense amplifier. For the data "1", the bit line BL is set at Vcc. For the data "0", the bit line BL is set at Vss. A voltage of (1/2)Vcc=BL-PL or a voltage of (-1/2)Vcc=BL-PL is applied to the cells. The data "1" moves from the point C to the point A, the data "0" stays at the point C, and the data is written.
The scheme shown in FIG. 3B slightly differs from that shown in FIG. 3C in the subsequent operation. In FIG. 3B, after the bit line BL is equalized to (1/2)Vcc (more specifically, the data "1" moves from the point A to the point B, and the data "0" moves from the point C to the point D), the word line WL is closed to return the bit line potential to 0V. Even when the bit line BL is equalized, the data stays at the point B or D, so the data is not destroyed. This operation reversely exploits the characteristics of the ferroelectric capacitor. In FIG. 3C, after the word line WL is closed, the bit line BL is equalized to (1/2)Vcc (more specifically, the data "1" stays at the point A, and the data "0" stays at the point C). For reading after recall, the charge difference (Ps-Pr) between the point A and the point B or between the point C and the point D is used, as in the DRAM (the degradation in the amount of the remnant polarization Pr due to the fatigue caused by polarization inversion in reading is suppressed).
The scheme shown in FIG. 3B or 3C is more advantageous than that shown in FIG. 3A in that the operation speed in access time or cycle time does not degrade unlike the scheme of changing the plate electrode potential, so that a high-speed operation is enabled. On the other hand, the scheme shown in FIG. 3B or 3C is more disadvantageous than that shown in FIG. 3A in that the voltage (coercive voltage Vc) necessary for polarization inversion must be (1/2)Vcc or less (this problem is solved by reducing the size of the ferroelectric film). Additionally, the FRAM has a large disadvantage in that a refresh operation is required, like the DRAM (the refresh operation increases the stand-by current or generates a busy rate).
In the scheme shown in FIG. 3B, the storage node SN of the cell is at (1/2)Vcc in the stand-by state. When the storage node potential becomes lower than (1/2)Vcc due to the leakage current at the p-n junction or the like, the data "1" moves from the point B to the point C, and the data is destroyed. Accordingly, the refresh operation must be performed to select the word line WL and write the potential of (1/2)Vcc in the storage node SN every a predetermined period in the stand-by state, as shown on the right side of FIG. 3B.
In the scheme shown in FIG. 3C, the storage node SN is set at Vcc or 0V in the stand-by state. When the storage node potential becomes lower than Vcc due to the leakage current at the p-n junction or the like, the data "1" moves from the point A to the point B, and then to the point C, and the data is destroyed. In this case, since the normal operation is the same as that of the DRAM, the data is destroyed upon moving to the point B. Accordingly, the refresh operation must be performed to select the word line WL and read/sense/rewrite the data every predetermined period in the stand-by state, like the DRAM, as shown on the right side of FIG. 3C.
For the conventional DRAMs, various cells are developed to realize a cell size smaller than 8F.sup.2. A stacked-type transistor or stacked-type TFT (Thin Film Transistor) is used to realize a size of 4F.sup.2, or cell transistors are connected in series, and capacitors are connected between the cell transistors and the plate electrode PL, thereby realizing a size of about 4F.sup.2 (NAND cell).
Since the equivalent circuit of the FRAM is basically the same as that of the DRAM, an FRAM having a size of 4F.sup.2 can be realized with the same cell structure as that of the DRAM. The FRAM also has the same problems as those of the DRAM. The stacked-type transistor or stacked-type TFT can hardly be realized because the manufacturing process is more complex than that for a conventional planar transistor having a size of 8F.sup.2, which can be easily manufactured. In the FRAM, these cells are basically realized as trench cells in which a transistor is formed after the ferroelectric capacitor process. Therefore, the permittivity of the ferroelectric capacitor decreases due to the heat process in the transistor manufacturing process.
The NAND cell can be manufactured using a planar transistor and can have a stack cell structure in which the capacitor is formed after the transistor process. In the NAND cell, however, cell data must be sequentially read out from cells closer to the bit line BL or must be sequentially written in cells farther from the bit line BL. This degrades the random access properties as an important point of a general-purpose memory and allows only block read/write access.
As described above, in the conventional FRAM, when a memory cell having a size of 4F.sup.2 smaller than 8F.sup.2 is to be realized, the process becomes complex for, e.g., the stacked-type transistor, or the random access properties of a general-purpose memory degrade for, e.g., a NAND cell. Additionally, the conventional FRAM cannot simultaneously realize the high-speed operation of the scheme of fixing the plate electrode potential and omission of the refresh operation.
Various systems having semiconductor memories have examined replacement of the conventional DRAM with the FRAM. However, such examinations have not reached a practical level yet because of the above-described problems unique to the FRAM.